This invention relates generally to digital to analog converters. More particularly, the invention relates to switched R-2R ladder networks.
The functional operation of a digital to analog converter (DAC) is well known. Generally, a DAC accepts an digital input signal and converts it into an analog output signal. The digital input signal has a range of digital codes which are converted into a continuous range of analog signal levels of the analog output signal. DACs are useful to interface digital systems to analog systems. Applications of DACs include video or graphic display drivers, audio systems, digital signal processing, function generators, digital attenuators, precision instruments and data acquisition systems including automated test equipment.
There are a variety of DACs available for converting digital input signals into analog output signals depending upon the desired conversion functionality. The variations in the DACs available may have different predetermined resolutions of a digital input signal, receive different encoded digital input signals, have different ranges of analog output signals using a fixed reference or a multiplied reference, and provide different types of analog output signals. Additionally there are a number of DAC performance factors to consider such as settling time, full scale transition time, accuracy or linearity, and a factor previously mentioned, resolution.
The digital input signal is a number of bits wide that defines the resolution, the number of output levels or quantization levels and the total number of digital codes that are acceptable. If the digital input signal is m-bits wide, there are 2m output levels and 2mxe2x88x921 steps between levels. The digital input signals may be encoded in straight binary, two""s complement, offset binary, grey scale code, binary coded decimal or other digital coding. The range of analog output signal values usually depend upon an analog reference. The analog reference may be internally generated but is usually externally provided for precision. The analog output signal range may be proportional to the digital input signal over a fixed analog reference level as in a fixed reference DAC. Alternatively, the analog output signal may be the product of a varying input analog reference level and the digital code of the digital input signal as in multiplying DACs. The analog output signal may be unipolar ranging in either positive values or negative values or it may be bipolar ranging between both positive and negative output values. The analog output signal may be an analog voltage signal or an analog current signal.
Additionally, the type of electronic circuitry used to form a DAC varies as well. Bipolar junction transistor (BJT) technology, metal oxide semiconductor (MOS) technology or a combination thereof are used to construct DACs. BJT technology may be PNP technology with PNP transistors or NPN with NPN transistors or both, while MOS technology may be PMOS with P-channel field effect transistors (PFET), NMOS with N-channel field effect transistors (PFET) or CMOS technology having both PFETs and NFETs.
Referring now to FIG. 1A, a block diagram of a DAC 100 has a digital input signal DIN 101, a positive analog supply voltage level AVref+ 104, and a negative analog supply voltage level AVrefxe2x88x92 105 in order to generate an analog voltage output signal AVout 110. Alternatively DAC 100 can generate an analog current output signal with minor changes to its circuit configuration. For simplicity in discussion consider DAC 100 to be a fixed reference DAC such that the output voltage range of AVout 110 is a function of DIN 101 and the range of voltage is defined by the predetermined voltage levels of AVref+ 104 and AVrefxe2x88x92 105. DIN 101 is m bits wide. The predetermined value of m represents the range of decimal numbers that DIN 101 will represent. The selected circuitry for DAC 100 varies depending upon a number of factors including power supply inputs and desired parameters of input and output signals. As illustrated in FIG. 1A, DAC 100 includes a signal converter 112 and an amplifier or buffer 114. Some forms of DACs, specifically current output DACs, may not include the buffer 114 and require external amplification. Signal converter 112 converts DIN 101 into a form of analog signal, VLADR 102, which is input to buffer 114. Buffer 114 buffers the analog signal VLADR 102 generated by the signal converter 112 from a load that may be coupled to AVout 110. The signal converter 112 includes a switched R-2R ladder 116 and a switch controller 118. Switch controller 118 controls switches within the switched R-2R ladder 116 to cause it to convert the value of DIN 101 into an analog signal.
As previously discussed, there are a number of DAC performance factors to consider including a DAC""s accuracy or linearity. Referring now to FIGS. 1B and 1C, graphs of bipolar output voltages for AVout 110 and unipolar output voltages for AVout 110 as a function of the digital input signal DIN 101 are illustrated. Transfer curves 120-121 represent the ideal transfer characteristics of a DAC for converting DIN into AVout. Transfer curves 122-123 represent the actual measured transfer characteristics of a DAC for converting DIN into AVout. The difference between the ideal transfer curves 120-121 and the actual transfer curves 122-123 is the integral linearity of a DAC. If a change in an analog voltage reference level is required to establish a zero point or a midpoint of the conversion range it is referred to as an offset voltage. Differential linearity is the linearity between code transitions measuring the monotonicity of a DAC. If increasing code values of DIN results in increasing values of AVout, the DAC is monotonic, and if not, the DAC has a conversion error and is not monotonic. The linearity of a DAC is very important for accurate conversions and is usually specified in units of least significant bits (LSB) of the m-bits of DIN. Linearity of a DAC can vary over temperature, voltages, and from circuit to circuit. Additionally, DAC linearity becomes more important as the predetermined DAC resolution is increased where the value of m is larger and additional digital codes are desired to be converted. Furthermore, as the analog voltage reference level range between AVref+ 104 and AVrefxe2x88x92 105 may be increased to accommodate additional resolution, it is desirable to maintain linearity in a DAC.
Referring now to FIG. 2A, a prior art switched R-2R ladder 116 is illustrated. The switched R-2R ladder 116 is a 4 bit inverted R-2R ladder to provide an analog voltage output signal but may be easily expanded to m-bits with the addition of other intermediate R-2R switch legs and additional switch control lines. Alternatively, a non-inverted R-2R ladder could be used to provide an analog current output signal. Signals DBn/DBp 201 are selectively controlled by the switch controller 118 in order to generate an analog voltage output signal VLADR 102. DBn/DBp 201 switches ON and OFF NFETs 211-214 and PFETs 216-219 in order to change the voltage division of the R-2R resistor network between AVref+ 104 and AVrefxe2x88x92 105 and VLADR 102. Inverters 246-249 generate the inverter polarity of the switch control lines D4Bp-D1Bp 241-244 to control the NFETs 236-239 to form fully complementary switches with PFETs 216-219. NFET 211 and PFET 216/NFET 236 represent the MSB of the DAC and can couple {fraction (8/16+L )} of the reference voltage range to VLADR 102. NFET 212 and PFET 217/NFET 237 can couple {fraction (4/16+L )} of the reference voltage range to VLADR 102. NFET 213 and PFET 218/NFET 238 can couple {fraction (2/16+L )} of the reference voltage range to VLADR 102. NFET 214 and PFET 219/NFET 239 represent the LSB of the DAC and can couple {fraction (1/16+L )} of the reference voltage range to VLADR 102. Thus, when the digital code is 1111, PFETs 216-219 and NFETs 236-239 are all ON and NFETs 211-214 are all OFF such that {fraction (15/16+L )} of the reference voltage range is coupled to VLADR 102. When the digital code is 0000, NFETs 211-214 are all ON and PFETs 216-219 and NFETs 236-239 are all OFF such that no current flows between AVref+ 104 and AVrefxe2x88x92 105 in a resistor and AVrefxe2x88x92 105 is coupled to VLADR 102.
The circuit connections of the switched R-2R ladder 116 are now described. NFET 215 has its gate tied to terminal leg gate voltage signal, TLGV 235, such that it is constantly turned ON. The voltage level of TLGV 235 additionally provides switch resistance matching between NFETs and PFETs in the switched R-2R ladder 116. NFETs 211-215 have sources connected to AVrefxe2x88x92 105 and drains respectively connected to first ends of resistors 220-224. PFETs 216-219 have sources connected to AVref+ 104 and drains respectively connected to first ends of resistors 220-223. NFETs 236-239 have sources respectively connected to the first ends of resistors 220-223 and drains connected to AVref+ 104. The gates of NFETs 211-214 are respectively connected to signals D4Bn-D1Bn 231-234 and gates of PFETs 216-219 are respectively connected to signals D4Bp-D1Bp 241-244 of DBn/DBp 201. The inverters 246-249 have inputs respectively coupled to signals D4Bp-D1Bp 241-244 to generate the inverted polarity for coupling their outputs to the gates of NFETs 236-239 respectively. Signals D4Bn-D1Bn 231-234 and signals D4Bp-D1Bp 241-244 are collectively referred to as signals DBn/DBp 201 from switch controller 118. Resistors 220-223 each have a resistance value of 2R. Resistors 224-228 each having a resistance value of R are coupled in series together with a first end of resistor 228 coupled to VLADR 102. A second end of resistor 224 is coupled to a second end of resistor 225 at node 250 while a second end of resistor 220 is coupled to VLADR 102. Resistors 223, 225, and 226 each have an end coupled to node 251. Resistors 222, 226, and 227 each have an end coupled to node 252. Resistors 221, 227, and 228 each have an end coupled to node 253. The MSB leg of the switched R-2R ladder 116 is defined as NFET 211/PFET 216/NFET 236 and resistor 220, the LSB leg as NFET 214/PFET 219/NFET 239 and resistors 223 and 226, and the termination leg as NFET 215 and resistors 224-225. The intermediate legs of the switched R-2R ladder 116 are NFET 213/PFET 218/NFET 238 and resistors 222 and 227 and NFET 212/PFET 217/NFET 237 and resistors 221 and 228.
As previously discussed, linearity of DAC 100 is important to accurately convert DIN 101 to AVout 110. In switching voltages in the switched R-2R ladder 116, PFETs 216-219, NFETs 236-239 and NFETs 211-214 are switched ON to operate in their linear region where drain to source voltage is equivalent to drain to source current times the ON resistance of the transistor. VDS≈IDSxc3x97RON. The drain to source voltage and drain to source current vary such that the ON resistance RON of the transistor may remain somewhat constant. FIG. 2B illustrates idealized output characteristic of an NFET. The y-axis represents drain to source current IDS and the x-axis represents drain to source voltage VDS. The curves 260-263 are generated respectively by applying increasing levels of gate to source voltage VGS to the NFET. The PFETs 216-219, NFETs 236-239 and NFETs 211-214 preferably operate in the linear or triode region 264 before going into saturation which is represented by saturation curve 265. The saturation curve 265 represents the saturation voltage from drain to source where VDSsat≈VGSxe2x88x92VT where VT is the threshold voltage for a given MOSFET device. In the linear region a rough estimate of current is provided by the equation IDS=Kxe2x80x2(W/L)[VGSxe2x88x92VTxe2x88x92(VDS/2)]VDS where Kxe2x80x2 is a device constant. In saturation this current equation can be reduced to IDSsat=(xc2xd)Kxe2x80x2(W/L)[VGSxe2x88x92VT]2 when VDS=VDSsat≈VGSxe2x88x92VT. Thus, IDSsat is relatively constant over variations in VDS once saturation occurs such that the resistance of the transistor remains high and relatively constant up until a drain to source breakdown voltage is reached. Reference designators 266-269 illustrate breakdown of a MOSFET such that for little change in drain to source voltage the drain to source current increases substantially. In breakdown, the device resistance is very small and substantial damage may occur if the drain to source current is not limited.
Additionally, PFETs and NFETs are binarilly weighted from LSB to MSB to adjust for differences in IDS drain to source current flow and maintain similar VDS voltage drops across drain to source. For example, if NFET 214/PFET 219/NFET 239 switches are weighted 1xc3x97, NFET 213/PFET 218/NFET 238 switches are weighted 2xc3x97, NFET 212/PFET 217/NFET 237 switches are weighted 8xc3x97, and NFET 211/PFET 216/NFET 236 switches are weighted 16xc3x97 in transistor size to reduce the RON of the transistors. This reduces user trimming for a drift that would otherwise be introduced by mismatched RON resistances when the transistor switches are turned ON and OFF.
NFET 215 is provided in the termination leg and is weighted 1xc3x97 to match RON of the other switches in the other legs of the switched R-2R ladder 116 and to match device temperature coefficients as well. Preferably, NFET 215 operates in its linear region 264 as well. However, there are circumstances that may cause NFET 215 to go into saturation and no longer operate in its linear region such that it limits the drain to source current flow to a relatively constant value and cause DAC output errors. When DIN 101 is such that PFET 219/NFET 239 are ON and NFET 214 is OFF, the LSB series circuit of PFET 219/NFET 239, resistors 223-225 and NFET 215 is completed. This causes an incrementally larger amount of drain to source current to flow through NFET 215 because of the relatively lower resistance between AVref+ 104 and AVrefxe2x88x92 105. Furthermore, under this condition a higher voltage must be dropped across the drain and source of NFET 215 such that it can cause NFET 215 to incrementally increase towards the saturation region causing linear degradation of the DAC 100. Additionally, if DIN 101 is set to full scale, such as 1111, additional drain to source current is required to flow through NFET 215. These conditions are exacerbated when the reference voltage range, (AVref+ 104)-(AVrefxe2x88x92 105), is greater than the VDSAT of NFET 215; or the VDSAT of NFET 215 is less than the reference voltage range because of the manufacturing process or other operating voltages; or a higher resolution of DAC is desirable thereby generating additional drain to source current flow and drain to source voltage drop across NFET 215 such that non-linearity in a DAC can occur. If the voltage across NFET 215 is even greater, the transistor can go into breakdown causing transistor inoperability and possibly permanent circuit damage. In order to design higher resolution DACs, accommodate wider ranges of reference voltages and maintain DAC linearity, it is desirable to improve the switched R-2R ladder 116 such that these conditions are reduced and NFET 215 operates in its linear region over a wider range of operating conditions.
Briefly, the present invention includes a method, apparatus and system for digital to analog converters with improved switched R-2R ladders as described in the claims. Switched R-2R ladders are improved by increasing the resistance in series with the termination switch in the termination leg. The switched R-2R ladder circuit is modified to compensate for increasing resistance in the termination leg in order to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal. The increased resistance in the termination leg causes a larger voltage to be dropped across it thereby reducing the voltage dropped across the termination switch and thus preserving its linear operation.